View XRP7720EVB-DEMO-1_8871551.PDF datasheet online --- IC-ON-LINE

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x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m january 2014 rev. 1.0.0 exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668 - 70 00 C fax. +1 510 668 - 70 01 general description the xrp 7720 is a quad output universal customizable pmic comprised of a quad channel digital pulse width modulated ( d pwm) step down (buck) controller and 5v ldo . a wide 4.75v to 5.5v and 5.5v to 18 v input voltage dual range allows for single supply operation from standard power rails. it is pin compatible to the popular xrp7724 and provides full flexibility during the development phase while offering a cost effectiv e option for high volume production units. with integrated fet gate drivers , it can operate from 105khz to 1.23mhz with independent channel - to - channel programmab le operating frequency , the xrp 7720 reduces overall component count and solution footprint whil e optimizing conversion efficiencies. a selectable digital pulse frequency mode (dpfm) and low operating current result in better than 80% efficiency down to 10ma load provides support for portable and energy star compliant applications. each xrp 7720 output channel is individually programmable down to a minimum 0.6v with a resolution of 2.5mv, and configurable for precise soft start and soft stop sequencing, including delay and ramp control. during development, t he xrp 7720 ilb - dev is configured using po werarchitect tm 5.1 (pa 5.1) through an i 2 c interface , allowing for short development of the power system and short time to market for the entire system. once development is completed and volume production is ready to commence, exar will assign a unique pa rt suffix and deliver a customized xrp7720 . built - in independent output over voltage, over temperature, over - current and under voltage lockout protections ensure safe operation under abnormal operating conditions. the xrp 7720 is offered in a rohs compliant , green/ halogen free 44 - pin tqfn package. features ? pin compatible to xrp7724 ? smbus compliant i 2 c interface available on xrp7720ilb - dev only ? supported by powerarchitect? 5.1 ? xrp7720ilb - dev only ? quad channel step - down c ontroller ? digital pwm 105khz - 1.23mhz operation ? individu al channel frequency selection ? patented digital pfm with ultrasonic mode ? integrated mosfet drivers ? programmable 5 coefficient pid control ? 4.75v to 18 v input voltage ? 4.75v - 5.5 and 5.5v - 18 v input range ? 0.6v to 5.5v output voltage ? 3 x 15v capable psio s + 2 x gpios ? full start/stop sequencing support ? built - in thermal, over - current, uvlo and output over - voltage protections ? on board 5v standby ldo ? 7x7mm tqfn44 package applications ? blade servers ? micro servers ? network adapter card s ? switches/routers ? video surveillance systems
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m january 2014 rev. 1.0.0 exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668 - 70 00 C fax. +1 510 668 - 70 01 typical application diagram figure 1 xrp 7720 application diagram x r p 7 7 2 0 + + + + 5 v v o u t 2 v o u t 3 3 . 3 v + + v o u t 4 1 . 0 5 v v i n 3 0 0 k h z 3 0 0 k h z 1 . 2 m h z + + 1 . 5 v v o u t 1 6 0 0 k h z g l _ r t n 2 g l 2 l x 2 b s t 2 g h 2 g l _ r t n 3 g l 3 l x 4 b s t 3 g h 3 g l _ r t n 4 g l 4 l x 4 b s t 4 g h 4 g l _ r t n 1 g l 1 l x 1 b s t 1 g h 1 v o u t 1 v o u t 2 v o u t 3 v o u t 4 v c c l d o 5 v 5 e x t d v d d ( 1 . 8 v ) a v d d ( 1 . 8 v ) 5 v ( o p t i o n a l ) e n p s i o 0 p s i o 1 p s i o 2 g p i o 0 g p i o 1 v c c d 1 - 2 v c c d 3 - 4 v i n 5 v 5 v v i n l d o 5 l d o 5 g n d ( s c l x r p 7 7 2 0 - d e v o n l y ) g n d ( s c a x r p 7 7 2 0 - d e v o n l y )
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation confidential 3 / 28 rev. 1.0.0 features and benefit s programmable power benefits ? fully configurable ? output set point ? feedback compensation ? frequency set point ? under voltage lock out ? reduced development time with xrp7720 - dev ? configurable and re - configurable for different vout, iout, cout, and inductor values ? no need to change external passives for a new output specification. ? higher integration and reliability ? many external circuits used in the past can be eliminated thereby significantly improving reliability. ? pin compatible to xrp7724 ? provides easy migration path to a full fea tured programmable power management system with dynamic control and telemetry ? powerarchitect? 5.1 design and configuration software ? wizard quickly generates a base design ? calculates all configuration registers ? projects can be saved and recalled ? gpios can be configured easily and intuitively ? dashboard interface can be used for real - time monitoring and debug ( - dev only) system integration capabilities ? single supply operation ? 5 gpio pins with a wide range of configurability ? fault reporting (including uvlo w arn/fault, ocp warn/fault, ovp, temperature, soft - start in progress, power good, system reset) ? allows a logic level interface with other ics or as logic inputs to other devices ? selectable switching frequency between 105khz and 1.2mhz ? internal mosfet driver s ? internal fet drivers (4/2) per channel ? built - in automatic dead - time adjustment ? 30ns rise and fall times ? 4 independent smps channels and standby ldo in a 7x7mm tqfn
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 4 / 28 rev. 1.0.0 absolute maximum rat ings these are stress ratings only and functio nal operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. vccd, ldo 5 , gl x , vout x .......................... - 0.3v to 7 .0v enable, 5v_ext ................................ ....... - 0.3v to 7 .0v gpio0/1, scl, sda ................................ ............... 6.0v psios inputs ................................ ......................... 18v dvdd, avdd ................................ ........................ 2.0v v cc ................................ ................................ ....... 23v lx# ................................ ............................. - 1v to 2 3 v bstx, ghx ................................ .................... vlxx + 6v storage temperature .............................. - 65c to 150c junction temperature ................................ .......... 150c power dissipation ................................ internally limited lead temperature (soldering, 10 sec) ................... 300c esd rating (hbm - human body model) .................... 2kv operating ratings input voltage range v cc ............................... 5.5v to 18 v input voltage range v cc = ldo5 ................ 4.75v to 5.5 v vout1, 2, 3, 4 ................................ ...................... 5.5v juncti on temperature range .................... - 40c to 125 c jed ec thermal resistance ja .......................... 30 .2 c/w electrical specifications specifications with standard type are for an operating junction temperature of t j = 25c only; limits applying over the full operating junction temperature range are denoted by a ?. typical values represent the most likely parametric norm at t j = 25c, and are provided for reference purposes only. unless otherwise indicated, v cc = 5.5 v to 18 v, 5v ext open . q uiescent c urrent parameter min. typ. max. units conditions v cc supply current in shutdown 10 20 a en = 0v, v cc = 12v enable turn on threshold 0 .82 0.95 v v cc = 12v enable rising enable pin leakage current 10 ua en=5v - 10 ua en=0v v cc supply current in standby 440 600 a all channels disabled gpios programmed as inputs v cc =12v,en = 5v v cc supply current 4ch pfm 4.0 ma 4 channels on set at 5v, vout forced to 5.1v, no load, non - switching, ultra - sonic off, v cc =12v , no i 2 c activity. v cc supply current on 18 ma all channels enabled, fsw =600khz, gate drivers unloaded , no i 2 c activity.
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 5 / 28 rev. 1.0.0 i nput v oltage r ange and u ndervoltage l ockout parameter min. typ. max. units conditions v cc range 5.5 18 v ? 4.75 5.5 v ? with v cc connected to ldo5 v oltage f eedback a ccuracy and o utput v oltage s et p oint r esolution parameter min. typ. max. units conditions vout regulation accuracy low output range 0.6v to 1.6v pwm operation - 5 5 mv 0.6 vout 1. 6 v - 20 20 mv ? - 7.5 7.5 mv 0.6 vout 1.6v v cc =ldo5 - 22.5 2 2.5 mv ? vout regulation accuracy mid output range 0.6v to 3.2 v pwm operation - 15 15 mv 0.6 vout 3.2 v - 45 45 mv ? - 20 20 mv 0.6 vout 3.2 v v cc =ldo5 - 50 50 mv ? vout regulation accuracy high output range 0.6v to 5.5v pwm operation - 30 30 mv 0.6 vout 5.5v - 90 90 mv ? - 40 40 mv 0.6 vout 4.2v v cc =ldo5 - 100 100 mv ? vout r egulation r ange 0.6 5.5 v ? vout set point resolution 1 2.5 5 10 mv low range mid range high range vout input resistance 120 90 75 k? low range mid range high range vout input resistance in pfm operation 10 1 0.67 m? low range mid range high range power good and ovp set point range (from set point) - 155 - 310 - 620 157.5 315 630 mv low range mid range high range power good and ovp set point accuracy - 5 - 10 - 20 5 10 20 mv low range mid range high range note 1: fine set point resolution not available in pfm
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 6 / 28 rev. 1.0.0 f ault s and w arnings parameter min. typ. max. units conditions current limit accuracy - 3.75 1.25 3.75 m v low range (120mv) - 60mv applied - 10 10 mv ? - 5 2.5 5 m v high range ( 280mv ) - 150mv applied - 12.5 +12.5 mv ? current limit set point resolution 1.25 mv low range (120mv) 2.5 mv high range ( 280mv ) current limit set point range - 120 20 mv low range (120mv) - 280 40 high range ( 280mv ) v cc uvlo set point range 4.6 18 v v cc uvlo set point resolution 200 mv v cc warn and fault s et point accuracy - 400 400 mv v cc uvlo warn (note 2) 4.4 4.72 v uvlo warn set point 4.6v, v cc =ldo5 over temperature set point resolution 5 c over temperature set point accuracy - 10 10 c note 2 : this test is only performed when warn is programmed to 4.6v . l inear r egulator parameter min. typ. max. units conditions ldo5 output voltage 4.85 5.0 5.15 v ? 5.5 v v cc 18 v 0ma < i ldo 5 out < 13 0ma , ldo3_3 off ldo5 current limit 1 05 12 5 15 0 ma ? ldo5 fault set ldo5 uvlo 4.74 v ? v cc rising ldo5 pgood hysteresis 375 mv v cc falling ldo5 bypass switch r esist ance 1.1 1.5 bypass switch activation threshold 2.5 2.5 % ? v5ext rising , % of threshold setting bypass switch activation hysteresis 150 mv v5ext falling maximum total ldo loading during enable start - up 30 ma enable transition from logic low to high. once ldo5 in regulation above limits apply.
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 7 / 28 rev. 1.0.0 pwm g enerators and o scillator parameter min. typ. max. units conditions switching frequency ( fsw ) range 105 1230 khz steps defined in table fsw accuracy C 5 5 % gpio s 3 parameter min. typ. max. units conditions i nput pin low level 0.8 v input pin high level 2.0 v input pin leakage current 1 a output pin low level 0.4 v i sink = 1ma output pin high level 2.4 v i source = 1ma output pin high level 3.3 3.6 v i source = 0ma output pin high - z leakage current (gpio pins only) 10 a maximum sink current 1 ma open drain mode i/o frequency 30 mhz note 3 : 3.3v cmos logic compatible , 5v tolerant . psio s 4 parameter min. typ. max. units conditions input pin low level 0.8 v input pin high level 2.0 v input pin leakage current 1 a output pin low level 0. 4 v i sink = 3ma output pin high level 15 v open drain. external pull - up resistor to user supply output pin high - z leakage current (p s io pins only) 10 a i/o frequency 5 mhz note 4 : 3.3v/5.0v cmos logic compatible, maximum rating of 15.0v g ate d rivers parameter min. typ. max. units conditions gh, gl rise time 17 ns a t 10 - 90% of full scale, 1nf c load gh, gl fall time 11 n s gh, gl pull - u p on - state output resistance 4 5 ? gh, gl pull - d own on - state output resistance 2 2.5 ? gh, gl pull - down resistance in off - m ode 50 k? v cc = vcc d = 0v. bootstrap diode forward resistance 9 ? @ 10ma minimum on time 50 ns 1nf of gate capacitance minimum off time 125 ns 1nf of gate capacitance
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 8 / 28 rev. 1.0.0 block diagram figure 2 xrp 7720 block diagram ldo block diagram figure 3 xrp 7720 ldo block diagram b s t 1 g p i o 0 - 1 c h a n n e l 1 g h 1 v c c g l 1 l x 1 g l _ r t n 1 l d o 5 h y b r i d d p w m d i g i t a l p i d f e e d b a c k a d c v r e f d a c p r e s c a l e r 1 / 2 / 4 s s & p d c u r r e n t a d c d e a d t i m e g a t e d r i v e r v o u t 1 v c c d 3 - 4 c h a n n e l 3 c h a n n e l 4 m u x v t j 5 v l d o g p i o i 2 c ( - d e v o n l y ) s d a , s c l n v m c l o c k p w r g o o d c o n f i g u r a t i o n r e g i s t e r s v o u t 3 v o u t 4 f a u l t h a n d l i n g o t p u v l o o c p o v p l o g i c p s i o 0 - 2 p s i o v c c d 1 - 2 e n a b l e c h a n n e l 2 v o u t 3 s e q u e n c i n g i n t e r n a l p o r v c c 4 u a 5 v l d o 1 . 8 v r e g u l a t o r l d o 5 5 v b l o c k s p s i o 1 . 8 v d i g i t a l v c c + - v 5 e x t 4 . 7 5 v C 4 . 9 v 3 . 3 v r e g u l a t o r 3 . 3 v g p i o g a t e d r i v e r s v c c d 1 - 2 d v d d 1 . 8 v a n a l o g a v d d v c c d 3 - 4
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 9 / 28 rev. 1.0.0 pin assignment figure 4 xrp 7720 pin assignment ( - dev only) pin description name pin number description v cc 41 input voltage. place a decoupling capacitor close to the controller ic. this input is used in uvlo fault generation. dvdd 16 1.8v supply input for digital circuitry. connect pin to avdd. place a decoupling capacitor close to the controller ic. vccd 1 - 2 vccd3 - 4 23,34 gate drive supply. two independent gate drive supply pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. one of the two pins must be connected to the ldo5 pin to enable two power rails initially. it is recommended that the other vccd pin be connected to the output of a 5v switching rail (for improved efficiency or for driving larger external fets), if available, otherwise this pin may also be connected to the ldo5 pin. a bypass capacitor (>1uf) to pad is recommended for each vccd pin with the pin(s) connected to ldo5 with shortest possible length of etch . agnd 2 analog ground pin. this is the small signal ground connection. gl_rtn1 - 4 39,33, 28,22 ground connection for the low side gate driver. this should be routed as a signal trace with gl. connect to the source o f the low side mosfet. gl 1 - gl 4 38,32, 27,21 output pin of the low side gate driver. connect directly to the gate of an external n - channel mosfet. 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 4 2 5 2 0 1 9 1 7 1 8 1 6 1 5 1 3 1 4 1 2 1 0 1 2 3 4 5 6 7 8 9 3 6 3 7 3 9 3 8 4 0 4 1 4 3 4 2 4 4 2 1 3 5 n / c a g n d n / c a v d d v o u t 1 v o u t 2 v o u t 4 g p i o 0 g p i o 1 g l 2 l x 2 g h 2 b s t 2 g l _ r t n 3 g l 3 l x 3 g h 3 b s t 3 v c c d 3 - 4 g n d ( s c l ) p s i o 1 p s i o 2 d v d d p s i o 0 d g n d b s t 4 g h 4 l x 4 g l 4 l d o 5 v 5 e x t g n d v c c e n a b l e g l 1 l x 1 g h 1 b s t 1 v c c d 1 - 2 v o u t 3 e x p o s e d p a d : a g n d x r p 7 7 2 0 t q f n 7 m m x 7 m m 1 1 g n d ( s d a ) 2 3 g l _ r t n 2 3 4 g l _ r t n 1 2 2 g l _ r t n 4
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 10 / 28 rev. 1.0.0 name pin number description gh 1 - gh 4 36,30, 25,19 output pin of the high side gate driver. connect directly to the gate of an external n - channel mosfet. lx 1 - lx 4 37,31, 26,20 lower supply rail for the gh high - side gate driver. connect this pin to the switching node at the junction between the two external power mosfets and the inductor. these pins are also used to measure voltage drop acr oss bottom mosfets in order to provide output current information to the control engine. bst 1 - bst 4 35,29, 24,18 high side driver supply pin(s). connect bst to the external capacitor as shown in the typical application circuit on page 2 . the high side dri ver is connected between the bst pin and lx pin and delivers the bst pin voltage to the high side fet gate each cycle. gpi0 - gpio1 9,10 these pins may be configured as inputs or outputs to implement custom flags, power good signals, enable/disable controls and synchronization to an external clock. ps io 0 - ps io 2 13,14,15 open drain, these pins may be used to control external power mosfets to switch loads on and off, shedding the load for fine - grained power management. they may also be configure d as standard logic outputs or inputs just as any of the gpios can be configured, but as open drains they will require an external pull - up when configured as outputs. gnd 11, 12 xrp7720ilb - xxxx - f. these pins should be tied to ground. sda, scl 11,12 xrp7720ilb - dev - f only. smbus/i 2 c serial interface communication pins for communication to powerarchitect tm 5.1 using xrp77xxevb - xcm (exar configuration module). accommodation should be made in the board layout to tie these pins to ground for production. vout 1 - vout 4 5,6, 7,8 connect to the output of the corresponding power stage. the output is sampled at least once every switching cycle ldo 5 44 output of a 5v ldo. this is a micro power ldo that can remain active while the rest of the ic is in standby mode. this ldo is al so used to power the internal analog blocks. enable 40 if enable is pulled high or allowed to float high, the chip is powered up (logic is reset, registers configuration loaded, etc.). the pin must be held low for the xrp7720 to be placed into shutdown. dgnd 17 digital ground pin. this is the logic ground connection, and should be connected to the ground plane close to the pad. v5 ext 43 external 5v that can be provided. if one of the output channels is configured for 5v, then this voltage can be fed ba ck to this pin for reduced operating current of the chip and improved efficiency. avdd 4 output of the internal 1.8v ldo. a decoupling capacitor should be placed between avdd and agnd close to the chip. pad 45 this is the die attach paddle, which is exposed on the bottom of the part. connect externally to the ground plane. n/c 1,3,42 no connect ordering information part number temperature range marking package packing quantity note 1 xrp7720ilb - dev - f - 40ct j +12 5c xrp7720ilb yyw w lot# 44 - pin tqfn tray halogen free xrp7720ilbtr - xxxx - f * - 40ct j +12 5c xrp7720ilb yyww lot# 2.5 k/tape & reel halogen free xrp7720evb - demo - 1 xrp7720evb power board only xrp7720evb - demo - 1 - kit xrp7720evb power board, usb stick, xrp77xxevb - xcm, usb cable, ribbon connector yy = year C ww = work week *minimum order requirements apply; please contact your exar representative.
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 11 / 28 rev. 1.0.0 typical performance characteristics all data taken at v cc = 12v , t j = t a = 25c, unless otherwise specified - schematic and bom from xrp 772 4 evb. see xrp 772 4 evb - demo - 1 manual. fig ure 1 pfm to pwm transition fig ure 2 pwm to pf m transition fig ure 3 pfm zero current accuracy fig ure 4 ldo5 brown out recovery, no load fig ure 5 0 - 6a transient 300khz
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 12 / 28 rev. 1.0.0 fig ure 6 simultaneous start - up fig ure 7 sequential start - up fig ure 8 simultaneous shut down fig ure 9 sequential shut down fig ure 10 enable threshold over temp 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 -40c 25c 85c 125c vin=25v rising vin=25v falling vin=4.75 v rising vin=4.75 v falling vcc vcc vcc vcc
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 13 / 28 rev. 1.0.0 functional overview the xrp 7720 is a quad - output digital pulse width modulation (dpwm) controller with integrated gate drivers for use with synchronous buck switching regulators. each output voltage can be programmed from 0.6v to 5.5v without the need for an external voltage divider. th e wide range of programmable dpwm switching frequency (from 105 khz to 1.2 mhz) enables the user to optimize for efficiency or component sizes. since t he digital regulation loop requires no external passive components, loop performance is not compromised d ue to external component variation or operating condition. the xrp 7720 provides a number of critical safety features, such as over - current protection (ocp), over - voltage protection (ovp), over temperature protection (otp) plus input under voltage lock o ut ( uvlo). in addition, a number of key health monitoring features including warning level flags for the safety functions and various power good ( pgood ) functions which may be configured to the gpios for hardware monitoring . the above are all programmable duri ng the development phase through pa 5.1 when using the xrp7720ilb - dev. for hardware communication, the xrp 7720 has two logic level general purpose input - output (gpio) pins , three 15v, open drain, power system input - output (psio) pins , and an enable pin . two pins are dedicated to the smbus data (sda) and clock (scl) which are available in the xrp7720ilb - dev but are eliminated in the production version . if full dynamic control and telemetry are desired in the production system, the pin compatible xrp7724 is available. in addition to providing four switching outputs , the xrp 7720 also provides a stand - by linear regulator that produce 5v for a total of 5 customer usab le supplies in a single device. the 5v ldo is used for internal power and is also optionall y available to power external circuitry. the re is also a 1.8v linear regulator which is for internal use only and should not be used externally. a key feature of the xrp 7720 is its powerful power management and time to market capabilities through the use o f the xrp7720ilb - dev . during development, a ll four outputs are independently programmable which provides full control of the d elay, r amp, and s equence during power up and power down . additionally, this programmability allows control of the interaction of the outputs and power down in the event of a fault , including active ramp down of the output voltages to remove an output voltage as quickly as possible. t he outputs may also be defined and controlled as groups. the xrp 7720 ilb - dev and standa rd xrp7720ilb - x x xx - f provide two different types of programmable memory. the xrp7720ilb - dev has a rewritable non - volatile flash memory (nv fm ) that allows multiple re - configurations during development . in production, the xrp7720ilb - xx x x - f is factory program med in a one - time programmable memory . t he xrp 7720 bring s an extreme ly high level of functionality and performance to a programmable power system . ever decreasing product budgets require the designer to quickly make good cost/performance tradeoff s to be t ruly successful. by incorporating four switching channels, a n ldo, and internal gate drivers in a single package, the xrp 7720 allows for extremely cost effective power system designs. the key cost factor to consider in cost tradeoffs is the flexibility of the xrp7720ilb - dev during systems reliability testing. the programmable versatility of the xrp7720ilb - dev along with the lack of hard wired and on board configuration components allows for minor and major changes during development to be made in circuit and on the board , by simpl y reprogramming with pa 5.1 .
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 14 / 28 rev. 1.0.0 theory of operation c hip a rchitecture r egulation l oops fig ure 11 xrp 7720 regulation loop s figure 1 1 sho ws a simplified functional block diagram of the regulation loops for one output channel of the xrp7720 . there are 3 separate parallel control loops; pulse width modulation (pwm), pulse frequency modulation (pfm), and ultrasonic. each of these loops is fed by the analog front end (afe) as shown at the left of the diagram. the afe consist of an input voltage scalar, a programmable voltage reference (vref) dac, error amplifier, and a window comparator. some of the function blocks are common and shared by each cha nnel by means of a multiplexer. pwm loop the pwm loop operates in voltage control mode (vcm) with optional vin feed forward based on the voltage at the v cc pin . the reference voltage (vref) for t he error amp is created by a 0.15 v to 1.6v dac that has 12 .5mv resolution. in order to get a 0.6v to 5.5v output voltage range an input scalar is used to reduce feedback voltages for higher output voltages to bring them within the 0.15 v to 1.6v control range. f or output voltages up to 1.6v (low range) the scalar has a gain of 1. for output voltages from 1.6v to 3. 2v (mid range) the scalar gain is 1/2 and for voltages greater than 3. 2v (high range) the gain is 1/4 . this results in the low range having an output voltage resolution of 12.5mv, mid range of 25mv and the high range having a resolution of 50mv. the error amp has a gain of 4 and compares the output voltage of the scalar to vref to create an error voltage on its output. this is converted to a digital error term by the afe adc which is stored in the er ror register. the error register has a fine adjust function that can be used to improve the output voltage set point resolution by a factor of 5 resulting in a low range resolution of 2.5mv, mid range resolution of 5mv and a high range resolution of 10 mv. the output of the error re g ister is then used by the p roportional i ntegral d erivative (pid) controller to manage the loop dynamics . the xrp 7720 pid is a 17 - bit five coefficient control engine that calculates the correct duty cycle under the various operat ing conditions and feeds it to the digital pulse width modulator (dpwm). besides the normal coefficients , the pid also uses the vin voltage to provide a feed forward function. e r r o r a m p a f e a d c e r r o r r e g i s t e r p i d d p w m g a t e d r i v e r v r e f d a c s c a l a r 1 , 2 , 4 p f m / u l t r a s o n i c v i n f e e d f o r w a r d g h x g l x l x x p w m - p f m s e l c u r r e n t a d c w i n d o w c o m p . v f b ( v o u t x ) v i n ( v c c ) v d r i v e ( v c c d ) x f i n e a d j u s t a f e
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 15 / 28 rev. 1.0.0 the xrp 7720 dpwm includes a special delay timing loop that gives a timing resolu tion that is 16 times the master oscillator frequency (103mhz) for a timing resolution of 60 7 p s for both the driver pulse width and dead time delays . the dwpm creates and drives the gate high (gh) and gate low (gl) signals. the maximum and minimum on time s and dead time delays are programmable by configuration resisters. pfm mode loop the xrp7724 has a pfm loop that can be enabled to improve efficiency at light loads. by reducing switching frequency and operating in the discontinuous conduction mode (dcm), both switching and i 2 r losses are minimized. figure 1 2 shows a functional diagram of the pfm logic. fig ure 12 pfm enter/exit functional diagram the pfm loop works in conjunction with the pwm loop and is entered when the output current falls below a programmed threshold level for a programmed number of cycles. when pfm mode is entered, the pwm loop is disabled and instead, the scaled output voltage is compared to vref with a window comparator. the window comparator has three thresholds; normal (vref), high (vref + %high) and low (vref - %low). the %high and %low values are programmable and track vref. in pfm mode, the normal comparator is used to r egulate the output voltage. if the output voltage falls below the vref level, the comparator is activated and triggers the dpwm to start a switching cycle. when the high side fet is turned on, the inductor current ramps up which charges up the output capac itors and increasing their voltage. after the completion of the high side and low side on - times, the lower fet is turned off to inhibit any inductor reverse current flow. the load current then discharges the output capacitors until the output voltage falls below vref and the normal comparator is activated this then triggers the dpwm to start the next switching cycle. the time from the end of the switching cycle to the next trigger is referred to as the dead zone. when pfm mode is initially entered the switc hing duty cycle is the same that it was in pwm mode. the result is the inductor ripple current will remain the same as it was in pwm mode. during operation the pfm duty cycle is calculated based on the ratio of the output voltage to v cc . this method ensure s that the output voltage ripple is well controlled and is much lower than in other architectures which use a burst methodology. if the output voltage ever goes outside the high/low window s , pfm mode is exited and the pwm loop is reactivated. although th e pfm mode does a good job in improving efficiency at light load, at very light loads the dead zone time can increase to the point where the switching frequency can enter the audio hearing range. when this happens some components, like the output inductor and ceramic capacitors, can emit audible noise. the amplitude of the noise depends mostly on the board design and on the manufacturer and construction details of the components. proper selection of components can reduce the sound to very low levels. in ge neral ultrasonic mode is not used unless required as it reduces light load efficiency. ultrasonic mode ultrasonic mode is an extension of pfm to ensure that the switching frequency never enters the audible range. when this mode is entered, the switching f requency is set to 30khz and the duty cycle of the upper and lower fets, which are fixed in pfm mode, are decreased as required to keep the output # c y c l e s r e g d e f a u l t = 2 0 p f m c u r r e n t t h r e s h o l d r e g a a < b b i a d c c h x f s w a a < b b + - + - + - v r e f h i g h v r e f v r e f l o w v o u t q q r s p f m e x i t t r i g g e r p u l s e p f m m o d e p w m m o d e c o u n t e r c l e a r c l k
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 16 / 28 rev. 1.0.0 voltage in regulation while maintaining the 30khz switching frequency. under extremely light or zero load cu rrents, the gh on time pulse width can decrease to its minimum width. when this happens, the lower fet on time is increased slightly to allow a small amount of reverse inductor to flow back into vin to keep the output voltage in regulation while maintainin g the switching frequency above the audio range. i nternal d rivers the internal high and low gate drivers use totem pole fets for high drive capability . they are powered by two external 5v power pins (vccd1 - 2) and (vccd3 - 4) , vccd1 - 2 powers the drivers for channels 1 and 2 and vccd3 - 4 powers channels 3 and 4. the drivers can be powered by the internal 5v ldo by connecting their power pins to the ldo5 output through an rc filter to avoid conducted noise back into the analog cir cuitry. to minimize power dissipation in the 5v ldo , it is recommended to power the drivers from an external 5v power source either directly or by using the v5ext input . good quality 1u f to 4.7uf capacitors should be connected directly between the powe r pins to ground to optimize driver performance and minimize noise coupling to the 5v ldo supply. the driver output s should be connected directly to their corresponding output s witching fet s, with t he lx output connected to the drain of the lower fet for the best current monitoring accuracy. see anp - 32 practical layout guidelines for power xr designs ldo s the xrp 7720 has an internal low drop out (ldo) linear regulator that generate s 5.0v (ldo5) for both internal and external use. additionally it has a 1.8v regulator that supplies power for the xrp 7720 internal circuits . fig ure 3 shows a block diagram of the linear power supplies. ldo5 is the main power input to the device and is supp lied by an external 5.5v to 18 v ( v cc ) supply. the output of ldo5 should be bypassed by a good quality capacitor connected between the pin and ground close to the device . the 5v output is used by the xrp 7720 as a standby power supply and is also used to pow er the 3.3v and 1.8v linear regulators inside the chip and can also supply power to the 5v gate drivers. the total output current t hat the 5v ldo can provide is 10 0ma. the xrp 7720 consumes approximately 20ma and the rest can be used by the gate drive curr ents. during initial power up, the maximum external load should be limited to 30ma. the avd d pin is the 1.8v regulator output and needs to be connected externally to the dv d d pin on the device. a good quality capacitor should be connected between this pin and ground close to the package. for operation with a v cc of 4.75v to 5.5v, the ldo5 output needs to be connected directly to v cc on the board .
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 17 / 28 rev. 1.0.0 c locks and t iming fig ure 1 3 xrp 7720 timing block diagram figure 1 3 shows a simplified block d iagram of the xrp 7720 timings. again, p lease note that the function blocks and signal names used are chosen for ease of understanding and do not necessarily reflect the actual design. the system timings are generated by a 103mhz in ternal system clock (sys_clk). the basic timing architecture is to divide the sys_clk down to create a fundamental switching frequency (fsw_fund) for all the output channels that is settable from 105khz to 306khz. the switching frequency for a channel (fsw_chx) can then be selected as 1 times, 2 times or 4 times the fundamental switching frequency . to set the base frequency for the output channels a fsw_set value representing the base frequency shown in table 1 , is entered into the switching frequency configuration register . note that the fsw_set value is basically equal to the sys_clk divided by the base frequency. the system timings are then created by dividing down sys_clk to produce a base frequency clock, 2x and 4x times the base frequency clocks, and sequencing timing to position the output channels relative to each other. each output channel then has its own frequency multiplier register that is used to select its final output swi tching frequency. table 1 shows the available channel switching frequencies for the xrp 7720 device. in practice the pa 5.1 design tool handles all the details and the user only has to enter the fundamental switching frequency and the 1x, 2x, 4x frequency m ultiplier for each channel. base frequency khz available 2x frequencies khz available 4x frequencies khz 105.5 211.1 422.1 107.3 214.6 429.2 109.1 218.2 436.4 111.0 222.0 444.0 112.9 225.9 451.8 115.0 229.9 459.8 117.0 234.1 468.2 119.2 238.4 476.9 121.5 242.9 485.8 123.8 247.6 495.2 126.2 252.5 504.9 128.8 257.5 515.0 131.4 262.8 525.5 134.1 268.2 536.5 137.0 273.9 547.9 139.9 279.9 559.8 143.1 286.1 572.2 146.3 292.6 585.2 149.7 299.4 598.8 153.3 306.5 613.1 157.0 314.0 628.0 160.9 321.9 643.8 165.1 330.1 660.3 169.4 338.8 677.6 174.0 348.0 695.9 178.8 357.6 715.3 183.9 367.9 735.7 189.3 378.7 757.4 195.1 390.2 780.3 201.2 402.3 804.7 207.7 415.3 830.6 214.6 429.2 858.3 222.0 444.0 887.9 229.9 459.8 919.6 238.4 476.9 953.7 247.6 495.2 990.4 257.5 515.0 1030.0 268.2 536.5 1072.9 279.9 559.8 1119.6 292.6 585.2 1170.5 306.5 613.1 1226.2 table 1 p l l x 4 / x 8 r e g f r e q u e n c y s e t r e g d p w m t o c h a n n e l s 2 ? 4 s y s t e m c l o c k b a s e f r e q u e n c y 2 x 4 x c h 1 t i m i n g f r e g m u l t r e g s e l s e q u e n c e r
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 18 / 28 rev. 1.0.0 s upervisory and c ontrol power system design with xrp 7720 is accomplished using powerarchitect? design tool version 5 .1 (pa 5 .1 ). all figures referenced in the following sections are taken from pa 5 .1 . d igital i/o xrp 7720 has two general purpose input output (gpio) and three power system input output (psio) user configurable pins. ? gpios are 3.3v cmos logic compatible and 5v tolerant. ? psio configured as outputs are open drain and require external pull - up resistor. these i/os are 3.3v and 5v cmos logic compatible, and up to 15v capable. the polarit y of the gpio/psio pins is set in pa 5 .1 . configuring gpio/psios the following functions can be controlled from or forwarded to any gpio/psio: ? power group enable C controls enabling and disabling of group 1 and group 2 ? power channel enable C controls enabling and disabling of a n individual channel . ? power ok C indicates that selected channels have reached their target levels and have not faulted . multiple channel selection is available in which case the resulting signal is the and logic function of all channels selected ? resetout C is delayed power ok. delay is programmable in 1msec increments with the range of 0 to 255 msec ? low vcc C indicates when vcc has fallen below the uvlo fault threshold and when the uvlo condition clears (vcc voltage rises above the uvlo warning level) low vcc, power ok and resetout signals can only be forwarded to a single gpio/psio. in addition, the following are functions that are unique to gpio0 and gpio1. hw flags C these are hardware monitoring functions forwarded to gpio0 only. the functions inc lude under - voltage warning, over - temperature warning, over - voltage fault, over - current fault and over - current warning for every channel. multiple selection s will be combined using the or logic function .
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 19 / 28 rev. 1.0.0 ? hw power good C the power good hardware monito ring function. it can only be forwarded to gpio1. it is an output voltage monitoring function that is a hardware comparison of channel output voltage against its user defined power good threshold limits (power good minimum and maximum levels). it has no hy steresis. multiple channel selection s will be combined using the and logic function of all channels selected . ? the power good minimum and maximum levels are expressed as percentages of the target voltage. ? pgood max is the upper window and pgood min is the lower window. the minimum and maximum for each of these values can be calculated with the following equation: ????? ( % ) = ? ? ??? ( ?? ) ? 10 5 ??????? ( ? ) ? where n =1 to 63 for the pgood max value and n=1 to 62 for the pgood min value. for example, with the target voltage of 1.5v and set point resolution of 2.5mv (lsb), the power good min and max values can range from 0. 17 % to 10.3 % and 0.17% to 10.5% respectively . a user can effectively double the range by changing to the next higher o utput voltage range setting, but at the expense of reduced set point resolution. f ault h andling there are s even different types of fault handling: ? under voltage lockout (uvlo) mo nitors voltage supplied to the vcc pin and will cause the controller to shutdo wn all channels if the supply drops to critical levels. ? over temperature protection (otp) monitors temperature of the chip and will cause the controller to shutdown all channels if temperature rises to critical levels. ? over voltage protection (ovp) monitor s regulated voltage of a channel and will cause the controller to react in a user specified way if the regulated voltage surpasses threshold level. ? over current protection (ocp) monitors current of a channel and will cause the controller to react in a user specifi ed way if the current level surpasses threshold level. ? start - up time - out fault monitors whether a channel gets into regulation in a user defined time period ? ldo5 over current protection (ldo5 ocp) monitor s current drawn from the regulator and will cause the c ontroller to be res e t if the current exceeds ldo5 limit (155ma typical) uvlo both uvlo warning and fault levels are user programmable and set at 200mv increments in pa 5 .1 . when the warning level is reached the controll er will generate a flag if gpio0 is so configured (see the digital i/o section). when an under voltage fault condition occurs the xrp 7720 outputs are shut down . in addition, the host can be informed by forwarding the low vcc signal to any gpio/psio (see the digital i/o section). this signal transitions when the uvlo fault occurs. once the uvlo condition clears (vcc voltage rises a bove or to the user - defined uvlo warning level) the low vcc signal will transition and the controller will be reset. s pecial attention needs to be paid in the case when vcc = ldo5 = 4.75v to 5.5v. since the input voltage adc resolution is 200mv the uvlo warning and fault set points are coarse
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 20 / 28 rev. 1.0.0 for a 5v input. therefore, setting the warning level at 4.8v and the fault level at 4.6v may result in the outputs not being re - enable d until a full 5.0v is reached on vcc. setting the warning level to 4.6 v and the fault level at 4.4v will allow uvlo handing as desired . h owever, at a fault level below 4.6v , the device has a hardware u vlo on ldo5 to ensure proper shutdown of the internal circuitry of the controller. this means the 4.4v uvl o fault level will never occur. otp user defined otp warning, fault and restart levels are set at 5c increments in pa 5 .1 . when the warning level i s reached the controller will assert hw flags on gpio0 (see the digital i/o section). when an otp fault condition occurs, the xrp 7720 outputs are shut down . once temperature reaches a user defined otp restart threshold level, the controller will reset. ovp a user defined ovp fault level is set in pa 5 .1 and is expressed in percentages of a regulated target voltage. resolution is the same as for the target voltage (expressed in percentages). the ovp minimum and maximum values are calculated by the fol lowing equation where the range for n is 1 to 63 : ??? ( % ) = ? ? ??? ( ?? ) ? 10 5 ??????? ( ? ) when the ovp level is reached and the fault is generated, it can be monitored through gpio0. a user can choose one of three options on how to react to an ovp event: to shutdown the faulting channel, to shut down faulting channel and perform auto - restart of the channel, or to restart the chip. warning : choosing the restart chip o ption during development is not recommended as it makes debug efforts difficult . in the case of shutting down the faulting channel and auto - restarting, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the chann el) periods in 1 msec increments with a maximum value of 255 msec. note: the channel fault action response is the same for either the ovp or ocp event.
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 21 / 28 rev. 1.0.0 ocp a user defined ocp fault level is set with 1 0 ma increments in pa 5 .1 . pa 5 .1 uses calculations t o give the user the approximate dc output current entered in the current limit field . however the actual current limit trip value programmed into the part is limited to 280mv as defined in the electrical characteristics. the maximum value the user can program is limited by rdson of the synchronous power fet and current monitoring adc range. for example, using a synchronous fet with rdson of 30m? and wider adc range the maximum current limit programmed would be: ??? ??? ( ? ) = 280 ?? 30 ? = 9 . 33 ? the current is sampled approximately 30ns before the low side mosfet turns off so the actual measured dc output current in this example would be 9.33a plus approximately half the inductor ripple. an ocp fault is consi dered to have occurred only if the fault threshold has been tripped in four consecutive switching cycles. when the switching frequency is set to the 4x multiplier the current is sampled every other cycle. as a result it can take as many as 8 switching cy cles for an over current event to be detected. when operating in 4x mode an inductor with a soft saturation characteristic is recommended. in addition, ocp fault can be monitored through hw flags on gpio0. the ocp warning level is calculated by pa 5.1 as 85% of the ocp fault level. a user can choose one of three options in response to an ocp event: shut down the faulting channel, shut down faulting channel and perform auto - restart of the channel, or restart the chip. the output current reported by the xrp 7720 is processed through a 7 sample median filter in order to reduce noise. the ocp limit is compared against unfiltered adc output. in the case of shutdown and auto - restart c hannel the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of 255 msec. note: the channel fault action response is the same for either the ovp or ocp event. start - up time - out fault a channel will be at start - up time - out fault if it does not come - up in a time period specified in the startup timeout box . in addition a channel is at start - up timeout fault if its pre - bias configuration voltage is within a defined value too close to the target. ldo5 ocp when current is drawn from the ldo5 that exceeds the ldo5 current limit the controller will be reset. v5ext switchover the v5ext gives the user an opportunity to supply an external 5 volt rail to the contr oller in order to reduce the controllers power dissipation. the 5 volt rail can be an independent power rail present in a system or any of 7720 channels regulated to 5 volts and routed back to the v5ext pin. it is important to note that voltage to vcc mus t be applied all the time even after the switchover , in which
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 22 / 28 rev. 1.0.0 case the current drawn from vcc supply will be minimal. if the function is not used, it is recommend ed that the pin either be grounded or left floating . in conjunction , the function must be disa bled through register settings. v5ext switchover control the v5ext function is enabled in pa 5 .1 . the switchover thresholds are programmable in 50mv steps with a total range of 200mv. the v5ext switchover has a 150mv hysteresis. ldo5 automatically turns o ff when the external voltage is switched in and turns on when the external voltage drops below the lower threshold. c hannel c ontrol channels can be controlled i ndependently by any gpio/psio . channels will start - up or shut - down following transitions of signals applied to gpio/psios set to control the channels. in development , using the xrp7720ilb - dev an d pa 5.1 , control can always be overridden. regardless of whether the channels are control led independently or are in a group the ramp rates will be followed as specified (see the power sequencing section). p ower s equencing all four channels can be grouped together and will start - up and shut - down in a user defined sequence. selecting none mea ns channel(s) will not be assigned to any group and therefore will be controlled independently. group selection there are three groups: ? group 0 C is controlled by the chip enable. channels assigned to this group will come up with the enable signal being high ( plus an additional delay need ed to load configuration fr o m flash to run t ime registers ) , and will go down with the enable signal being low. since it is recommended to leave the enable pin floating in the applications when vcc = ldo5 = 4.75v to 5.5v, please contact exar for how to configure the channels to come up at the power up in this scenario. ? group 1 C can be controlled by any gpio/psio. channels assigned to this group will start - up or shut - down following transitions of a signal applied to the gpio/ psio set t o co ntrol the group. ? group 2 C can be controlled by any gpio/psio. channels as signed to this group will start - up or shut - down following
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 23 / 28 rev. 1.0.0 transitions of a signal applied to the gpio/psio set to control the group. start - up for each cha nnel within a group a user can specify the following start - up characteristics: ? ramp rate C expr essed in milliseconds per volt. ? order C position of a channel to come - up within the group ? wait pgood ? C selecting this option for a channel means the next channel in the order will not start ramping - up until this channel reaches the target level and its power good flag is asserted. ? delay C an additional time delay a user can specify to postpone a channel start - up with respect to the previous channel in the order. t he delay is expressed in milliseconds with a range of 0 msec to 255 msec. shut - down for each channel within a group a user can specify the following shut - down characteristics: ? ramp rate C expressed in milliseconds per volt. ? order C position of a channel to come - down within the group ? wait stop thresh ? C selecting this option for a channel means the next channel in the order will not start ramping - down until this channel reaches the stop threshold level. the stop threshold level is fixed at 600mv. ? delay C additional time delay a user can specify to postpone a channel shut - down with respect to the previous channel in the order. the delay is expressed in milliseconds with a range of 0 msec to 255 msec. p rogramming xrp 7720 xrp 7720 ilb - de v is a flash based device which means its configuration can be programmed into flash nvm and re - programmed a number of times. the purpose of this feature is to provide a means to fast development times. programming of flash nvm is done through pa 5 .1 .
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 24 / 28 rev. 1.0.0 by clicking on the flash button the user will start programming sequence of the design configuration into the flash nvm. after the programming sequence completes the chip will reset (if a utomatically reset after flashing box is checked) and boot the design configuration from the flash.
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 25 / 28 rev. 1.0.0 e nabling xrp 7720 xrp 7720 has a weak internal pull - up ensuring it gets enabled as soon as internal voltage supplies have ramped up and are in regulation. driving the enable pin low externally will keep the contro ller in the shut - down mode. a simple open drain pull down is the recommended way to shut the xrp 7720 down. if the enable pin is driven high externally to control the xrp 7720 coming out of the shut - down mode care must be taken to ensure the enable pin is dr iven high after vcc gets supplied to the controller. in the configuration , when vcc = ldo5 = 4.75v to 5.5v, disabling the device by grounding the enable pin is not recommended. it is recommend ed to leav e the enable pin floating and plac e the controller in the standby mode instead in this scenario. the standby mode is defined as the state when all switching channels are disabled, all gpio/psios are programmed as inputs, and system clock is disabled. in this state chip consumes 440ua typi cal. short duration enable pin toggled low short duration shutdown pulses to the enable pin of the xrp 7720 , which does not provide sufficient time for the ldo5 voltage to fall below 3.5v , can result in significant delay in re - enabling of the device. some examples below show ldo5 and enable pins: no load on ldo5, blue trace. recovery time after enable logic high is approximately 40ms. adding a 200 ohm load on ldo5 pulls voltage below 3.5v and restart is short. note that as v cc increases, the restart time falls as well. 5.5v input is shown as the worst case. since the enable pin has an internal current source, a simple open drain pull down is the recommended way to shut down the xrp 772 0 . a diode in series with a resistor between the ldo5 and enable pins may offer a way to more quickly pull down the ldo5 output when the enable pin is pulled low.
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 26 / 28 rev. 1.0.0 application informat ion t hermal d esign as a 4 channel controller with internal mosfet drivers and 5v gate drive supply all in one 7x7mm 44pin tqfn package, there is the potential for the power dissipation to exceed the package thermal limitations. the xrp 7720 has an internal ldo which supplies 5v to the internal circuitry and mosfet drivers during startup. it is generally expected that either one of the switching regulator outputs is 5v or another 5v rail is available in the system and connected to the 5vext pin. if there is no 5v available in the system, then the power l oss will increase significantly and proper thermal design becomes critical. for lower power levels using properly sized mosfets and the use of the internal 5v regulator as a gate drive supply is considered appropriate. l ayout guidelines refer to application note anp - 32 practical layout gu idelines for power xr designs , as well as anp - 35 for routing long distance gate drive traces.
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 27 / 28 rev. 1.0.0 package specificatio n 44 - pin 7x7mm tqfn
x x r r p p 7 7 7 7 2 2 0 0 q q u u a a d d o o u u t t p p u u t t u u n n i i v v e e r r s s a a l l c c u u s s t t o o m m i i z z a a b b l l e e p p m m i i c c w w i i t t h h p p f f m m ? 2014 exar corporation 28 / 28 rev. 1.0.0 revision history revision date description 1.0.0 01/ 31 /2014 initial release [ecn: 14 06 - 02 ] for further assistan ce email: customersupport@exar.com powertechsupport@exar.com exar technical documentation: http://www.exar.com/techdoc/default.aspx? e xar c orporation h eadquarters and s ales o ffices 48720 kato road fremont, ca 94538 C notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a users specific application. while the information in this pu blication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corpo ration is prohibited .

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